隨著互補式金屬氧化物半導體 (CMOS) 製程尺寸的下降，串音缺陷 (crosstalk defect) 已經成為積體電路故障的重要因素。因此，現今的積體電路測試必須考量串音瑕疵 (crosstalk fault)。這篇論文針對了單埠 (single-port) 及多埠 (multiple-port) 記憶體中位址及資料匯流排之最大侵略串音瑕疵 (maximal aggressor crosstalk faults) 提出了兩個測試演算法。就擁有m位元位址及n位元資料輸入/輸出匯流排之單埠 (single-port) 及多埠 (multiple-port) 記憶體而言，其測試演算法分別需要2m+6n+2及4m+12n+8個執行動作來涵蓋100%的串音瑕疵。此外，這篇論文更提出一用於單埠記憶體且可同時提供串音瑕疵測試及March-CW測試的內建自我測試電路 (BIST) 架構。使用TSMC 0.18um standard cell technology合成實現內建自我測試電路 (BIST)，就一個8k×32位元的單埠記憶體而言，此內建自我測試電路 (BIST) 設計需要額外支出的面積大約是2%，且其延遲時間大約是2.1ns。 With the scaling of CMOS technology, the crosstalk defect has become an important cause of failure in integrated circuit (IC) designs. Therefore, crosstalk faults must be considered in modern IC testing. This thesis presents two test algorithms for maximal aggressor crosstalk faults on address and data buses of single-port and multiple-port memories. The two test algorithms require 2m+6n+2 and 4m+12n+8 operations to cover 100% crosstalk faults for a single-port and multiple-port memories with m-bit addresses and n-bit data I/Os. A BIST scheme which can support the test algorithms for crosstalk faults and March-CW [1] test for single-port RAMs is also proposed. Experimental results show that the area overhead of the BIST design for an 8k×32-bit single-port memory is about 2%. The delay of the BIST synthesized with TSMC 0.18um standard cell technology is about 2.1ns.
